Fin field effect transistors (FinFETs) typically include a source region and a drain region interconnected by fins which serve as a channel region of the device and a gate that surrounds at least a portion of each of the fins between the source region and the drain region. Epitaxial deposition is typically used to form the source region and the drain region. As transistors continue to be reduced in size and have an increased number of transistors per unit of microchip, a metal-oxide semiconductor (MOS) FET (MOSFET) pitch of the transistors scales down (e.g., under 100 nm) and a thickness of a silicon nitride spacer of a gate structure also scales to provide a large enough contact area for a source/drain. A thinner spacer induces higher parasitic capacitance that can reduce processing speed. The parasitic capacitance may cause slower ring oscillator (RO) speed and eventually lower circuit working frequency. With higher effective capacitance (CEFF) of RO, circuit performance may degrade and there may be higher power consumption during dynamic operation. In order to reduce CEFF, low-k dielectrics, i.e., materials with a dielectric constant lower than silicon nitride, may be used to form the gate spacer. Typical low-k materials include SiBN, SiCN and SiBCN. Two integration processes can be used to integrate low-k dielectrics as a gate spacer. In a low-k spacer-first approach, after gate deposition and etch, a low-k dielectric is conformally deposited and then etched using an anisotropic etch process such as reactive ion etching (RIE). An issue with a low-k spacer first results in Carbon/Boron loss during spacer reactive ion etch (RIE) and epitaxial deposition, which can increase the value of K. Alternatively, a low-k spacer-last process can be used, where a sacrificial spacer, such as silicon nitride, is first formed, and is subsequently removed after all high temperature processes (typically >600° C.) in the integration flow are executed. The gap formed as a result of sacrificial spacer removal is then filled with a low-K dielectric. An issue with a low-k spacer-last is that the aspect ratio (a structure's height relative to its width) of the sacrificial spacer is too high, and it is not easy to etch down the sacrificial spacer without damaging the oxide inter-layer dielectric (ILD) and dummy polysilicon gate.